Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits

With the proliferation of portable devices and increasing levels of chip integration, reducing power consumption is becoming of paramount importance. We describe a technique to automatically synthesize gated clocks for nite-state machines (FSMs) to reduce power in the nal implementation. This technique recognizes self-loops in the FSM (either from the state diagram or from a synchronous network) and uses the function described by the self-loops to gate the clock. The clock activation function is then used as don't-care information to minimize the logic in the FSM for additional power savings. We applied these techniques to standard MCNC benchmarks and found an average reduction in power dissipation of 25%, at the cost of a 5% increase in area.